发明名称 Method of designing a logic circuit utilizing an algorithm based in C language
摘要 An algorithm C description describing an algorithm of computation or control of a logic circuit in a C language is split into a plurality of states in units of processing, and the execution order of the split processing is described as state transition, to generate a functional C description with a control description embedded therein. A clock description as the conception of time is inserted in the functional C description, to be converted into a RT level C description. The RT level C description is converted into a RT level description in HDL with an existing conversion tool.
申请公布号 US7062728(B2) 申请公布日期 2006.06.13
申请号 US20020167579 申请日期 2002.06.13
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 TOJIMA MASAYOSHI
分类号 G06F17/50;G06F9/45;H01L21/82 主分类号 G06F17/50
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