发明名称 Method and apparatus for delay line calibration
摘要 Sub-sampled signals are compared to determine time delay, calibration of delay elements, and other precise time domain measurements, based on properties of aliased signals produced by the sub-sampling. In one embodiment, flip-flops sub-sample an input signal and a delayed signal. A counter measures time delay between edges in the sub-sampled input and sub-sampled delayed signal. The time delay is determined and averaged over a measurement window, and then scaled to determine an amount of delay of the delayed signal. Means to calibrate a delay element inside a measurement device (e.g., Bit Error Ratio Tester), utilizing sub-sampling techniques to achieve precise measurements very quickly and without the need for factory calibration.
申请公布号 US7062733(B1) 申请公布日期 2006.06.13
申请号 US20020098246 申请日期 2002.03.15
申请人 SYNTHESYS RESEARCH, INC. 发明人 POSKATCHEEV ANDREI;HELMER TOM;VERITY ROB
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址