发明名称 Computer aided design systems and methods with reduced memory utilization
摘要 Methods, systems, software products analyze a circuit design with reduced memory utilization. Access to at least one block of the circuit design is detected. If the one block is not loaded within a circuit model of computer memory, a determination is made whether loading the one block into the circuit model would exceed a predefined maximum utilization of the computer memory. If loading the one block into the circuit model would exceed the predefined maximum utilization, one or more blocks from the circuit model are unloaded and the one block is loaded into the circuit model. If loading the one block into the circuit model would not exceed the predefined maximum utilization, the one block is loaded into the circuit model.
申请公布号 US7062727(B2) 申请公布日期 2006.06.13
申请号 US20030647598 申请日期 2003.08.25
申请人 HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. 发明人 KELLER S. BRANDON;ROGERS GREGORY DENNIS;ROBBERT GEORGE HAROLD
分类号 G06F17/50 主分类号 G06F17/50
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