| 摘要 |
A finite state machine (FSM) circuit including a random access memory (RAM) as the basic logical element and a multiplexer, which can be programmed to perform arbitrary sequences of events. The RAM is used as a state table and output states are fed back to determine the next memory location. The number of locations in the RAM is reduced in comparison with prior art devices, which minimises power consumed by a microprocessor implementing such an FSM. This reduction in the number of locations is possible because only relevant inputs to the RAM are selected. The circuit has both synchronous and asynchronous implementations.
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