发明名称 |
VSB RECEIVER |
摘要 |
The loop gain of an AGC circuit 7 and the loop gain of a clock regenerating circuit 6 are increased (the gain of an amplifier is increased, or the band of a loop filter is widened) until a synchronizing signal ( a segment synchronizing signal or a field synchronizing signal ) is detected. The loop gain of the AGC circuit 7 and the loop gain of the clock regenerating circuit 6 are decreased (the gain of the amplifier is decreased, or the band of the loop filter is narrowed) after the synchronizing signal is detected. Consequently, it is possible to make a reduction of a time period required until convergence processing is completed in the AGC circuit and the clock regenerating circuit compatible with an improvement of a ghost disturbance removal performance and accurate clock regeneration. |
申请公布号 |
CA2311968(C) |
申请公布日期 |
2006.06.13 |
申请号 |
CA19992311968 |
申请日期 |
1999.09.24 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LIMITED |
发明人 |
KONISHI, TAKAAKI;UEDA, KAZUYA;AZAKAMI, HIROSHI |
分类号 |
H04L27/06;H03L7/107;H04L27/08;H04N5/21;H04N5/44;H04N5/52;H04N7/015 |
主分类号 |
H04L27/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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