发明名称 |
Apparatus, method and digital-to-analog converter for reducing harmonic error power |
摘要 |
An apparatus, method and digital-to-analog converter (DAC) for reducing harmonic error power is provided, suitable for current-mode self-calibration DAC. Unit currents are calibrated one by one based on a reference value and the error distribution of the unit currents appears identical characteristic. According to the calibrated current error distribution, a shift shifts the input digital signal so that the error distribution of the unit current selected by the digital signal is monotonicity and not related to self-calibration current period. A coarse decoder decodes the digital signal as compensation decoding. The harmonic power related to the self-calibration current period is greatly reduced, which improves the signal to noise ratio.
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申请公布号 |
US7061412(B1) |
申请公布日期 |
2006.06.13 |
申请号 |
US20050160663 |
申请日期 |
2005.07.05 |
申请人 |
SUNPLUS TECHNOLOGY CO., LTD. |
发明人 |
WANG SHIAO-FENG;CHEN CHENG-YUAN |
分类号 |
H03M1/06 |
主分类号 |
H03M1/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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