发明名称 DATA PROCESSING SYSTEM VERIFICATION DEVICE, METHOD, AND PROGRAM
摘要 PROBLEM TO BE SOLVED: To provide a data processing system verification device and method and a program for expressing the function of a data processing system on a computer by a calculation model, and for using one or more shared buses for communication between functional block models, and for reproducing and verifying circumstances where any delay is generated in communication due to the congestion of the shared buses in the development of a data processing system such as an LSI. SOLUTION: This data processing system is provided with a bus model part 15, scheduled model parts 13 and 18 and a scheduler model part 16 for executing time management in using one or more shared buses for communication among functional block model parts 14, 17 and 19 by utilizing a calculation model 10A of a UT level with time information taken into consideration. An execution start time is managed for each unit processing by the bus model 15 so that it is possible to reproduce and quickly verify circumstances where delay is generated in communication due to the congestion of the shared buses. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006146332(A) 申请公布日期 2006.06.08
申请号 JP20040332011 申请日期 2004.11.16
申请人 SONY CORP 发明人 HASHIMOTO TAKEHISA
分类号 G06F17/50 主分类号 G06F17/50
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