| 摘要 |
A semiconductor memory device including a shift redundancy circuit with two buffer chains, two fuses connected to the shift redundancy circuit, a plurality of fuse cut-out detecting circuits for detecting cut-out status of the fuses, and two spare cell control circuits for controlling two spare memory cell rows, wherein word line control signals for controlling corresponding word lines connected to memory cells in a memory cell array are shifted upward and downward to control respective next word lines, thereby replacing two defective memory cell rows with the two spare memory cell rows.
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