发明名称 System and method for optimizing phase locked loop damping coefficient
摘要 An adjustable oscillator for dynamically optimizing a damping coefficient of a PLL circuit including a gain controlled oscillator circuit and a damping controller. The PLL circuit provides a loop control signal indicative of an error between first and second clock signals and generates a third clock signal which has a frequency which is a clock multiplier times the frequency of the second clock signal. The oscillator circuit has a control input receiving the loop control signal, a gain control input, and an output that provides the third clock signal. The damping controller has an input receiving the clock multiplier and an output providing a gain control signal to the gain control input of the oscillator circuit. The damping controller adjusts gain of the oscillator circuit in response to changes of the clock multiplier to minimize variation of the damping coefficient.
申请公布号 US2006119442(A1) 申请公布日期 2006.06.08
申请号 US20050297511 申请日期 2005.12.08
申请人 VIA TECHNOLOGIES, INC. 发明人 AZAM MIR S.;LUNDBERG JAMES R.
分类号 H03L7/00 主分类号 H03L7/00
代理机构 代理人
主权项
地址