| 摘要 |
PROBLEM TO BE SOLVED: To provide a layout design method for a semiconductor integrated circuit capable of reducing power consumption. SOLUTION: This method is provided with a process 100 for replacing at least a part of a logical block in pre-layout net list 1001 configured of an Lvt cell library with an Hvt cell library, a delay time analyzing process 200 for detecting a timing error in the pre-layout net list after replacement processing, a process 210 for repeatedly executing a processing for preferentially using the cell in the Lvt cell library with respect to at least a part of paths where a timing error occurs until the timing error is eliminated in the delay time analyzing process, a delay time analyzing process 500 for detecting the timing error in layout data, and a timing optimization process 510 for performing a processing including cell resizing for a cell, buffer insertion, and cell replacement in the corresponding path, when the timing error is detected in the delay analyzing process. COPYRIGHT: (C)2006,JPO&NCIPI
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