| 摘要 |
According to one embodiment, a method of test error detection for a wafer having a plurality of rows of integrated circuit (IC) chips is provided. The method includes determining that a first number of IC chips that are indicated as failing a test has increased from a first row to a second row immediately following the first row at least by a first threshold. The method also includes determining that a second number of IC chips that are indicated as failing the test has decreased from a previous row to a second row immediately following the previous row at least by a second threshold. The method also includes indicating that a group of one or more rows located between the first row and the second row includes one or more IC chips that have been tested incorrectly.
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