| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce a test cost by curtailing time required for a scan test with respect to a scan test circuit. <P>SOLUTION: As to this scan test circuit, the cycle of a clock in shift operation is made shorter than the cycle of the clock in capture operation. For example, the cycle of the clock in the shift operation is set at 20 nano-seconds while the cycle of the clock in the capture operation is set at 100 nano-seconds. The clock is supplied from an LSI tester outside an LSI via a clock terminal CLK and the cycle of the clock can be changed over in synchronization with the change of a scan enabling signal SCANEN on the LSI tester side. Time occupied by the shift operation is shortened to make it possible to shorten the time required for the scan test. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
