发明名称 DATA TRANSFER INTO A PROCESSOR CACHE USING A DMA CONTROLLER IN THE PROCESSOR
摘要 A computer system is disclosed. The computer system includes a host memory, an external bus coupled to the host memory and a processor coupled to the external bus. The processor includes a first central processing unit (CPU), an internal bus coupled to the CPU and a direct memory access (DMA) controller coupled to the internal bus to retrieve data from the host memory directly into the first CPU.
申请公布号 WO2006047780(A3) 申请公布日期 2006.06.08
申请号 WO2005US39318 申请日期 2005.10.27
申请人 INTEL CORPORATION;EDIRISOORIYA, SAMANTHA 发明人 EDIRISOORIYA, SAMANTHA
分类号 G06F15/78 主分类号 G06F15/78
代理机构 代理人
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