| 摘要 |
PROBLEM TO BE SOLVED: To obtain a clock signal generation circuit for recording data which can quickly perform pull-in to a wobble signal into a PLL by widening a lock range of the PLL of a phase comparator without use of a highly precise frequency comparator. SOLUTION: A phase detector 29 detects in which phase the edge of a wobble signal WBL does exist from the order of signals SA-SD outputted according to a status of a 1st frequency division clock signal Sfd1 and a 2nd frequency division clock signal Sfd2 at rise time of the wobble signal WBL based on the 1st frequency division clock signal Sfd1, and duty cycles of an up signal SPu and a down signal SPd which are output signals of the phase comparator 21 are adjusted so that the change of frequency of the clock signal for data recording WCLK may speed up in accordance with the result of detection. COPYRIGHT: (C)2006,JPO&NCIPI
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