| 摘要 |
The present invention provides a system for dynamically allocating addresses to devices ( 110, 120, 130 ) coupled to an integrated circuit bus ( 102 ). The system includes a master processor ( 101 ) and a plurality of slave processors ( 111, 121, 131 ) corresponding to the devices. The master processor is used for generating a plurality of addresses one by one which are different from each other, and sending an instruction to the integrated circuit bus in order to assign one of the plurality of addresses to one of the devices whose address is a default address at that time. Each of the plurality of slave processors includes a plurality of functions of: presetting an address of a corresponding device of the devices to the default address, retrieving the instruction and resetting the address of the corresponding device of the devices according to the instruction.
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