发明名称 Phase locked loop circuit
摘要 A circuit of the present invention applied for the PLL is disclosed. The circuit comprises a loop filter, a first charge pump, and a second charge pump. The loop filter includes a unit gain buffer, a first capacitor connected to the input terminal of the unit gain buffer and a ground, a second capacitor connected to the output terminal of the unit gain buffer and the ground, and a low pass filter consisting of a resistor and a third capacitor connected to the output terminal of the unit gain buffer. The first charge pump is coupled to the output terminal of the RC low pass filter, and the second charge pump coupled to the input terminal of the unit gain buffer in the loop filter. The second capacitor in loop filter circuit of the present invention and the improvement on the charge pump are improved the stability of the PPL and reduced the influence of the loop filter circuit by the unit gain buffer.
申请公布号 US2006119404(A1) 申请公布日期 2006.06.08
申请号 US20050294383 申请日期 2005.12.06
申请人 VIA TECHNOLOGIES, INC. 发明人 YEH TSE-HSIEN
分类号 H03L7/06 主分类号 H03L7/06
代理机构 代理人
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