| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device which can increase the speed of read/verify operations. <P>SOLUTION: A clamp circuit 18 is connected to one end of adjacent first and second bit lines BLe and BLo in a memory cell array 11, and a data cache 17 is connected to the other end. The first and second bit lines are selectively divided into plural by first and second switches Qswe and Qswo. A control circuit 13 controls the data cache, the clamp circuit, and the first and second switch elements. The clamp circuit or the data cache precharges the bit line to which a memory cell having the address to be written is connected, and the clamp circuit shields the rest of the bit lines. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
