| 摘要 |
A parallel compression test circuit of a memory device disperses peak current and reduce noise by operating input/output amplifiers at different timings in a parallel compression test mode. The parallel compression test circuit comprises an input/output amplification control unit for activating a plurality of input/output amplifiers connected to a selected bank in a normal mode, and activating the plurality of input/output amplifiers in each bank at different timings in a test mode.
|
