Two processor architecture supporting decoupling of outer loop and inner loop in video decoder

摘要

Presented herein are systems, methods, and apparatus for two processor architecture supporting decoupling of the outer loop and the inner loop in a video decoder. In one embodiment, there is presented a video decoder for decoding a data structure. The video decoder comprises an outer loop processor and an inner loop processor. The outer loop processor performs overhead processing for the data structure. The inner loop processor decodes the data structure.