| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an internal clock generation circuit for shortening time required for locking an internal clock signal to an external clock signal, and an analog synchronous mirror delay with a wide operation range and capable of responding to frequency variation of the clock signal. <P>SOLUTION: The internal clock generation circuit comprises a first delay mirror, a coarse locking block, a voltage controlled delay block, a second delay mirror and a fine locking block. The first delay mirror is activated to delay a predetermined buffering clock signal by a predetermined first mirroring time and provide the delayed buffering clock signal as a delayed clock signal. The first mirroring delay time is equal to a sum of predetermined first to third transmission delay times. The buffering clock signal is offset from the external clock signal by a first transmission delay time. The coarse locking block provides a predetermined analog synchronous clock signal using the buffering clock signal and the delayed clock signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
