| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a technique for conducting an individual function test corresponding to forced finish, and an efficient logic circuit verification technique of high quality capable of preparing intentionally even a test pattern paid with attention to constitution of a verification objective logic circuit, while automating logical verification for an LSI or a system including it. <P>SOLUTION: Information concerned in a hardware resource used in a function block is registered in a pre-stage for conducting the function test, and the registered information is released to finish execution of the function test forcibly, when a forced finish instruction is detected during the execution of the function test. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
