| 摘要 |
The present invention relates to a bit line barrier metal layer for a semiconductor device and a process for preparing the same, the process comprising: forming bit line contact on an insulation layer vapor-deposited on an upper part of a substrate so as to expose an ion implantation region; vapor-depositing a first barrier metal layer of a Ti film on the entire upper surface thereof; and vapor-depositing, on the upper part of the Ti film, a second barrier metal layer of a ZrB<SUB>2 </SUB>film having different upper and lower Boron concentrations, by RPECVD controlling the presence/absence of H<SUB>2 </SUB>plasma, wherein the barrier metal layer includes the Ti film, lower ZrB<SUB>2 </SUB>film and upper a ZrB<SUB>2 </SUB>film sequentially stacked between tungsten bit lines and ion implantation region of a semiconductor substrate. Therefore, the present invention can decrease contact resistance between tungsten bit lines and an ion implantation region by utilizing a ZrB<SUB>2 </SUB>film having near-amorphous film quality as a barrier metal of tungsten bit lines and thereby preventing diffusion of the dopant doped onto the ion implantation region of a substrate to the outside in a subsequent thermal treatment process, and at the same time, can reduce occurrence of parasitic capacitance between adjacent bit lines by decreasing a thickness of barrier metal layer, thus leading to improved characteristics of the semiconductor device. |
