| 摘要 |
A semiconductor memory device for performing a self-refresh operation based on an internal refresh request signal, the device comprising: a first detection unit (41a, 42a, 43a) including a first filter (14, 15, 16) for receiving an external access request signal and eliminating a noise component from the external access request signal, wherein the first detection unit detects transition of an output signal of the first filter and generates a first detection signal based on the detection; a second detection unit (41b, 42b, 43b) for receiving the external access request signal, detecting transition of the external access request signal, and generating a second detection signal based on the detection; a first address transition detection unit (46a) including a second filter (23) for receiving an external address signal and eliminating a noise component from the external address signal, wherein the first address transition detection unit detects transition of an output signal of the second filter and generates a first address detection signal based on the detection; a second address transition detection unit (46b) for receiving the external address signal, detecting transition of the external address signal, and generating a second address detection signal based on the detection; a first signal synthesizing circuit (44) connected to the first detection unit and the first address transition detection unit for performing a logical operation with the first detection signal and the first address detection signal and generating a first synthesizing signal based on a result of the logical operation; a second signal synthesizing circuit (49) connected to the second detection unit and the second address transition detection unit for performing a logical operation with the second detection signal and the second address detection signal and generating a second synthesizing signal based on a result of the logical operation; an arbiter (27) connected to the second signal synthesizing circuit for performing a logical operation with the second synthesizing signal and the internal refresh request signal and generating a determination signal based on a result of the logical operation, wherein the determination signal indicates which one of the external access request and the internal refresh request is to be given priority; and a main signal generator (28) connected to the first signal synthesizing circuit and the arbiter for generating a main signal from the first detection signal or the determination signal in accordance with the determination signal to control the internal circuit of the device.
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