| 摘要 |
A semiconductor memory device having a plurality of banks for stably performing a write with auto-precharge (WRA) command or a read with auto-precharge (RDA) command, including: a bank signal generation unit for generating an interrupt bank signal based on a bank address signal and a column address strobe (CAS) signal; a data access period detection unit for generating a data access period signal based on the CAS signal and a bit line disable signal; and a masking signal generation unit for generating a masking signal in order to controlling a logic level of an auto-precharge signal based on the data access period signal and the interrupt bank signal.
|
