发明名称 |
System and method for paralleling digital wrapper data streams |
摘要 |
A system and method are provided for paralleling data streams in a G.709 network of connected integrated circuits. The system comprises a demultiplexer for receiving a first digital wrapper data stream having a first data rate. The demultiplexer demultiplexes the first data stream into a second plurality of digital wrapper data streams having a second data rate, less than the first data rate. A second plurality of processors each accept a corresponding one of the second plurality of data streams and supply a processed data stream at the second data rate. The demultiplexer receives frame alignment signal bytes in the overhead of every first data stream frame and synchronizes frame alignment signal bytes in each of the second plurality of data streams to the frame alignment signal bytes in the first data stream.
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申请公布号 |
US7058090(B1) |
申请公布日期 |
2006.06.06 |
申请号 |
US20010023675 |
申请日期 |
2001.12.18 |
申请人 |
APPLIED MICRO CIRCUITS CORPORATION |
发明人 |
PLAYER ANDREW MARK;SORGI ALAN MICHAEL;BENDAK GEORGE BESHARA |
分类号 |
H04J3/04 |
主分类号 |
H04J3/04 |
代理机构 |
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代理人 |
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地址 |
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