| 摘要 |
In a bi-directional, self-synchronous bus for communication between semiconductor devices, a logic delay is provided as a flag to a state machine control for indicating that the bus is making a transition from a low to a high state. The logic delay causes the bus to adaptively idle until the bus settles, making it amenable for a wide variety of bus sizes and topologies. In this way, oscillation of the bus is avoided without slowing the speed of the state machine clock.
|
