FALSE-LOCK-FREE DELAY LOCKED LOOP CIRCUIT AND METHOD

摘要

A phase detector in a delay locked loop circuit operates to determine the status of propagation of a first pulse of a reference clock signal (CKref) through a delay line (21). A first control signal (DOWN) is produced a in response to represent a first time at which the first pulse has progressed entirely through the delay line (21) and a later second time at which a next second pulse of the reference clock signal (CKref) arrives at a first input of the phase detector (24A). The delay of the delay line (21) is reduced in response to the first control signal (DOWN). A second control signal (UP) is produced in response to the status to represent a third time at which the second pulse of the reference clock signal (CKref) arrives at the first input of the phase detector (24A) and a later fourth time at which the first pulse of the reference clock signal (CKref) has progressed to the end of the delay line (21) and is used to increase the delay of the delay line (21).