<p>A method (Figure 6) for testing a partially fabricated wafer comprising: providing a plurality of selectable devices under test (DUT) overlying a substrate of the wafer (600); biasing a second structure in proximity to the DUT having a first electrical state such that a first equivalent test structure is formed (602); determining a first parasitic parameter associated with the first equivalent test structure by applying a signal to the DUT while the second structure is in the first electrical state and measuring a response that is indicative of the first parameter (604); biasing the second structure to a second electrical state such that a second equivalent test structure is formed (606); determining a second parasitic parameter associated with the second equivalent test structure by applying a signal to the DUT while the second structure is in the second electrical state and measuring a response that is indicative of the second parameter (608).</p>
