An electronic device has a first module (50, 52) including adjustable first clock circuitry (54) and a second module including (64) non-adjustable second clock circuitry (66). An interface between the first and second modules has a buffer arrangement (60, 62). This enables an asynchronous interface to be provided between a central unit with non-adjustable clock circuitry and multiple units with pausible clocks.
申请公布号
WO2006056904(A2)
申请公布日期
2006.06.01
申请号
WO2005IB53699
申请日期
2005.11.10
申请人
KONINKLIJKE PHILIPS ELECTRONICS N.V.;VAN KAAM, KEES, M., M.;DIELISSEN, JOHN;GOOSSENS, KEES, G., W.
发明人
VAN KAAM, KEES, M., M.;DIELISSEN, JOHN;GOOSSENS, KEES, G., W.