LAYOUT VERIFICATION METHOD AND DESIGN METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING THE SAME

摘要

PROBLEM TO BE SOLVED: To provide a layout verification method for a semiconductor integrated circuit device capable of detecting correctly a damage which a gate receives, and to provide a design method for the semiconductor integrated circuit device which enhances more sufficient workability and higher reliability, by determining the directivity for a design modification so as to avoid a plasma charging damage while detecting correctly the damage which the gate receives. SOLUTION: The layout verification method can output an antenna value as an estimated value of the transistor gate damage on the basis of the antenna rate and the change rate of a plasma charging damage caused by the layout in the vicinity of the transistor gate. COPYRIGHT: (C)2006,JPO&NCIPI