Method for correcting timing error when designing semiconductor integrated circuit

摘要

A method for correcting a timing error in an integrated circuit that includes a plurality of layout blocks with identical configurations in the same hierarchical layer. The method includes matching the tolerance for when a timing error occurs for a cell in each layout block with a worst condition of one of the corresponding cells in the layout blocks, and inserting a timing adjustment cell within a range of the matched tolerance of each cell to adjust the timing error. This method ensures the correction of hold errors and setup errors in an integrated circuit designed with a hierarchical design technique.