发明名称 TDMA communications apparatus
摘要 A CPU of a TDMA communications apparatus examines whether a slot to be allocated for a next transmission is a first slot (S 1 ). If the slot to be allocated is the first slot, the CPU examines whether there are any slots already allocated by other stations within a Selection Interval SI in a frame in which the next transmission of own station is to be allocated referring to a slot map in a memory and finds out a free slot within Selection Interval SI (S 11 ). Then, the CPU allocates the free slot as a next transmit slot of the own station and sets the slot number of the free slot as the slot number of the next transmit slot (S 12 ). Then, the CPU examines whether a slot adjacent to the next transmit slot of the own station is allocated to any of the other stations (S 13 ). If either of the slots adjacent to the next transmit slot of the own station is already allocated to another station, the CPU examines a time-out value set by that station for the adjacent slot (S 15 ) and sets an initial time-out value differing from the time-out value set by the other station for the adjacent slot (S 16 ).
申请公布号 US2006114862(A1) 申请公布日期 2006.06.01
申请号 US20050287401 申请日期 2005.11.28
申请人 FURUNO ELECTRIC COMPANY LIMITED 发明人 HIRAOKA YASUSHI
分类号 H04B7/212;H04W28/26;H04W72/04;H04W74/04 主分类号 H04B7/212
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