| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory test circuit which can perform surely a high speed test of a whole user circuit including an on-chip-memory in a short time. SOLUTION: The memory test circuit is arranged in an on-chip-memory and performs a high speed test of the on-chip-memory, and is provided with two dummy memory cells in which a high level and a low level are stored previously, and a control circuit controlling an operation of reading of respective data from two dummy memory cells at the high speed test. And two dummy memory cells are arranged at a physical position in the on-chip-memory in which timing of reading data is later than a memory cell in which timing of reading data is the latest out of memory cells included in the on-chip-memory. COPYRIGHT: (C)2006,JPO&NCIPI
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