| 摘要 |
A phase locked loop (PLL) circuit automatically corrects the offset of the analog (especially active type) loop filter to improve the stability and precision of the locked clock or frequency signals. In addition to the general PLL circuit configuration having active type loop filter ( 30 ), the PLL circuit also has a frequency comparing circuit ( 42 ), a DAC controller ( 44 ) and a DAC (digital-to-analog converter) ( 46 ). In an offset measurement mode, the outputs of phase error detecting circuit ( 12, 14 ) and frequency error detecting circuit ( 18, 20 ) are cut, respectively, to establish locking in offset measurement locked loop ( 42, 44, 45, 30, 40 ). In this case, offset correction code (EDs) are identified and held. In normal mode, DAC controller ( 44 ) has offset correction code (ED) input to DAC ( 46 ), and DAC ( 46 ) sends offset correction signal (EAs) to loop filter ( 30 ).
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