| 摘要 |
A plurality of error holding latches built in CPU cores 14-1, 14-2 formed on an LSI chip 10 are connected and constituted into a line of error collecting scan chain 48, and the interior of the error collecting scan chain is divided into CPU latch groups 56-1, 56-2 corresponding to the CPU cores 14-1, 14-2, and mask circuits 58-1, 58-2 are provided at the test operating time, which allow the latch content of the error holding latch group 56-1, 56-2 corresponding to a degenerated CPU core 14-1, 14-2 in the interior of two CPU cores to be masked, and the error collecting scan chain 48 is scanned out at the error occurrence time, thereby collecting error information. A latch group 56-3 and mask circuit 58-3 corresponding to a secondary cache 16 may be provided also.
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