发明名称 Logic-in-memory circuit using magnetoresistive element
摘要 A TMR network 120 using TMR elements as magnetoresistive elements is formed as a variable resistive element network by a series-parallel connection of two kinds of variable resistive elements R with resistance values that change according to an external input X or a memory input Y, as shown in an AND operation network 122 in FIG. 5 (b), wherein the total resistance value R<SUB>total </SUB>is minimized, that is, the current I is maximized for a particular combination of the inputs. Assuming R<SUB>xi </SUB>and R<SUB>yi </SUB>(i=0, 1 and 2) as the resistance values of the variable resistive elements R according, respectively, to the external input X and memory input Y, the values of x and y determine the current I that flows through the network as shown in FIG. 5 (d). Setting a threshold value between I<SUB>0 </SUB>and I<SUB>1 </SUB>using a threshold detector 160 makes it possible to realize AND operation. The operation result is then output as a voltage value through an IV converter 170.
申请公布号 US7054190(B2) 申请公布日期 2006.05.30
申请号 US20040914807 申请日期 2004.08.10
申请人 TOHOKU TECHNO ARCH CO., LTD. 发明人 HANYU TAKAHIRO;KIMURA HIROMITSU
分类号 G11C11/14;G11C11/00;G11C11/15;H01L21/8246;H01L27/10;H01L27/105;H01L43/08;H03K19/18 主分类号 G11C11/14
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