| 摘要 |
<p>The invention relates to analogue/digital converters (ADC) with an architecture comprising upstream (CRAM) and downstream (CRAV) cascading folding circuits with an interpolation circuit (CI) disposed between said two folding circuits. In order to prevent conversion errors owing to the presence of the interpolation circuit, a gain compensation stage (ATT) is disposed downstream of said interpolation circuit, which acts on some of the outputs of the interpolation circuit in order to ensure that all of the signals leaving the circuit have the same variation slope (as a function of the input voltage Vin to be converted), before they are applied to the downstream folding circuit. The gain compensation circuit preferably comprises a simple attenuator with a resistor network.</p> |
