CO-SIMULATION OF A PROCESSOR DESIGN

摘要

A technique of the present invention includes performing a simulation according to a processor co-simulation model (40) of a processor. Once form of this model is implemented by simulating execution of a sequence of instructions with an instruction set architecture simulator (62), storing respective instruction information in a queue (66) for each of the instructions simulated, and determining execution timing behavior of the sequence of instructions by simulating instruction execution with a microarchitecture simulator (70) as a function of the respective instruction information read from the queue (66) for each one of the instructions.