INTERNAL CLOCK GENERATING CIRCUIT WITH HIGH LOCKING SPEED AND ANALOG SYNCHRONOUS MIRROR DELAY BEING ADOPTABLE FOR THE SAME,申请号KR20040096059-传众专利搜索

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发明名称	INTERNAL CLOCK GENERATING CIRCUIT WITH HIGH LOCKING SPEED AND ANALOG SYNCHRONOUS MIRROR DELAY BEING ADOPTABLE FOR THE SAME
摘要
申请公布号	KR20060057034(A)	申请公布日期	2006.05.26
申请号	KR20040096059	申请日期	2004.11.23
申请人	SAMSUNG ELECTRONICS CO., LTD.	发明人	LEE, JAE YOUNG
分类号	H03L7/00	主分类号	H03L7/00
代理机构		代理人
主权项
地址

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