| 摘要 |
PROBLEM TO BE SOLVED: To provide an image processor capable of suppressing sharp increase in built-in memories necessary for interpolation processing and of reducing the chip cost of an LSI. SOLUTION: A vertical direction processing part 68 for performing vertical interpolation processing is constituted of line delay control part 74, multipliers 75 to 78, a coefficient generator 79, and an adder 81. A line delay control part 74 is constituted of connecting three line buffers in series. Inputted pixel data are delayed by respective line buffers. The line delay control part 74 is provided with a selector for selecting the inputted pixel data and pixel data outputted from respective output terminal of respective line buffers and outputting the selected pixel data. Respective pixel data selected by the selector and outputted from the line delay control part 74 to signal lines 0 to 3 are multiplied by an interpolation coefficient calculated by the coefficient generator 79 by using the multipliers 75 to 78 and the adder 81 to generate interpolated pixel data. COPYRIGHT: (C)2006,JPO&NCIPI |
