发明名称 Parallel data path architecture for high energy efficiency
摘要 Provided is a parallel data path architecture for high energy efficiency. In this architecture, a plurality of parallel process units and a plurality of function units of the process units are controlled by instructions and processed in parallel to improve performance. Also, since only necessary process units and function units are enabled, power dissipation is reduced to enhance energy efficiency. Further, by use of a simple instruction format, hardware can be programmed as the parallel data path architecture for high energy efficiency, which satisfies both excellent performance and low power dissipation, thus elevating hardware flexibility.
申请公布号 US2006112258(A1) 申请公布日期 2006.05.25
申请号 US20050144703 申请日期 2005.06.06
申请人 YANG YIL S;ROH TAE M;LEE DAE W;LEE SANG H;KIM JONG D 发明人 YANG YIL S.;ROH TAE M.;LEE DAE W.;LEE SANG H.;KIM JONG D.
分类号 G06F15/00 主分类号 G06F15/00
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