发明名称 Multi-chip package using an interposer
摘要 A method and apparatus for multi-chip packages that are closely coupled using an interposer is disclosed. A top single chip or multi-chip encapsulated package with bottom side contacts is formed and tested. A bottom single chip or multi-chip package substrate having bottom contacts is formed. Then a hollow center interposer is connected to the periphery of the package substrate leaving the chips at the center exposed, and the hollow region is filled with an encapsulant to the level of the top of the interposer, to form the finished package having contact on the bottom and on the top. After the bottom package undergoes electrical function testing, the top package is soldered to the interposer forming a completed multi-chip package.
申请公布号 US2006108676(A1) 申请公布日期 2006.05.25
申请号 US20040994984 申请日期 2004.11.22
申请人 PUNZALAN NELSON V JR;ESTINOZO MARCELINO IAN W 发明人 PUNZALAN NELSON V.JR.;ESTINOZO MARCELINO IAN W.
分类号 H01L21/48;H01L23/02 主分类号 H01L21/48
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