发明名称 |
DIGITAL CIRCUIT POWER SUPPLY VOLTAGE CONTROL SYSTEM |
摘要 |
<P>PROBLEM TO BE SOLVED: To provide a technique of reducing digital noise when a digital circuit is in operation in a system wherein an analog circuit and the digital circuit are integrated on one and same semiconductor substrate. <P>SOLUTION: The system is configured such that the system is provided with a clock signal generating circuit comprising components the same as those of the digital circuit, a power supply voltage of the digital circuit is adjusted on the basis of a phase difference between an output signal from the clock signal generating circuit and a reference signal for reduction of the digital noise so as to reduce the effect on the analog circuit integrated on the one and same semiconductor substrate as the digital circuit thereby preventing quality deterioration in the reception sensitivity or the like in a communication system. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
申请公布号 |
JP2006135438(A) |
申请公布日期 |
2006.05.25 |
申请号 |
JP20040319791 |
申请日期 |
2004.11.02 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
YOKOTA TETSURO;SHIMAZU TAKAYUKI |
分类号 |
H04B15/00;H03K5/26;H03L7/08 |
主分类号 |
H04B15/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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