发明名称 |
Programmable low-power high-frequency divider |
摘要 |
Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also described is a circuit included in the homologue frequency divides and a method for correcting the duty cycle of clock signals generated by the homologue frequency dividers to 50%.
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申请公布号 |
US2006109947(A1) |
申请公布日期 |
2006.05.25 |
申请号 |
US20060325786 |
申请日期 |
2006.01.05 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
AUSTIN JOHN S.;KELKAR RAM;THIAGARAJAN PRADEEP |
分类号 |
H03K21/00 |
主分类号 |
H03K21/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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