| 摘要 |
The present invention relates to an integrated memory device including: memory cells arranged at wordlines and bitlines, wherein the memory cells are addressable in sets of 2<SUP>n </SUP>bit, wherein n is an integer, a pre-fetch read unit to pre-fetch an addressed set of 2<SUP>n </SUP>data bit in parallel from the addressed memory area, buffer memory to buffer the number of pre-fetched data bits; a number m of output ports to output the data bits buffered in the buffer memory; an output controller for controlling the outputting of the data bits buffered in the buffer memory to the number m of output ports in groups of m bits in one or a plurality of successive cycles, characterized in that the number m of output ports is different to any of the possible numbers 2<SUP>n </SUP>of the sets of addressable memory cells.
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