发明名称 Eliminating systematic process yield loss via precision wafer placement alignment
摘要 A method for a semiconductor process includes correlating yield loss for the performance of a processing step in a semiconductor manufacturing process with the mechanical placement of the semiconductor substrate and, based on the correlation, placing semiconductor substrates in a position with sufficient placement precision to reduce yield loss below a predetermined threshold.
申请公布号 US2006110836(A1) 申请公布日期 2006.05.25
申请号 US20040992982 申请日期 2004.11.19
申请人 INFINEON TECHNOLOGIES RICHMOND, LP 发明人 DEVANY CHRISTOPHER;VENDITTI CHARLES E.
分类号 H01L21/00 主分类号 H01L21/00
代理机构 代理人
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