| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To speed up read operation with almost no increase in a chip area. <P>SOLUTION: An EEPROM is equipped with a memory cell array which is constituted with a block by disposing a plurality of NAND cells composed of nonvolatile memory elements so as to share a source line and is placed with a plurality of the blocks so as to share a bit line on one end side and to share the source line on the other end side, a column decoder which selects the bit lines of the memory cell array, and a row decoder which performs word line selection of the memory cells and gate line selection of a selection transistor. The gate lines SG2 of the source line side selection transistors adjoining between the respective blocks are commonly connected and are connected by the same contact to the wiring driven by the row decoder. The row decoder selects the gate lines SG2 of the source line side selection transistors adjoining between the blocks as one set. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
