| 摘要 |
Main memory units (MU) are each composed of an even number of sub memory units (SU) having different addresses. The sub memory units have memory cells (MC), bit lines corresponding to different data terminals with numbers, sense amplifiers, and column switch circuits for connecting the bit lines to data bus lines. Column switch areas (CSW) of the main memory units are formed in mirror symmetry and comprise four transistors each to provide common use of the global data bus lines (GDB) for read and write operations.
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