Register-addressing method for addressing a processor's registers addresses a register memory with numerous registers through a corresponding number of physical register addresses

摘要

An allocation unit has an allocation table (242) with a first area (FA) (244), in which possible logical page numbers (LPN) are represented for a first two-bit-dimension address section. There are four different LPN that assume values of 0, 1, 2 and 3. Each LPN in the FA is assigned a physical page number (PPN) in a second area (246). An independent claim is also included for a device for addressing a processor's registers.