发明名称 Arrangement for generating a clock signal for a sigma-delta analog-to-digital converter
摘要 In a method for generating a scanning clock signal (S) for scanning an analog signal (Ua) for an analog-to-digital converter ( 20 ) operating according to the sigma-delta method, a variable period (T; T*) of the power supply system (PL) is ascertained in time units of a system clock signal (C), and the scanning clock signal (S) is generated by distributing a constant number K of pulses over the ascertained period (T; T*), so that the frequency of the scanning clock signal (S) is an integer multiple of the frequency of the power supply system (PL). The method is essentially able to be carried out by an accumulator unit ( 4 ) connected to a counter ( 3 ) and makes possible the advantage that during the analog-to-digital conversion a mains hum contained in the analog signal (Ua) is suppressed.
申请公布号 US7049987(B2) 申请公布日期 2006.05.23
申请号 US20040900027 申请日期 2004.07.26
申请人 SIEMENS BUILDING TECHNOLOGIES AG 发明人 STOLL WALTER
分类号 H03M3/00;H03L7/00;H03M1/00 主分类号 H03M3/00
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